This invention relates to homogeneous parallel systems, and particularly to the execution of a homogeneous parallel program on a heterogeneous set of processor cores.
Processor chips typically have multiple processor cores, each capable of running one or more software program threads at a time. The number of hardware threads that can be running simultaneously on the chip is the total number of cores multiplied by the multithreading capability of each core. Many such processors present to the software a homogeneous view of the hardware capability, with each hardware thread being capable of running any software thread, so that neither the application nor the operating system needs to be concerned about the specific allocation of processors to threads.
A typical program seldom uses all the resources of a processor simultaneously. Some never use significant portions of the processor, e.g. the floating point units or the multimedia vector units. Some programs use certain functions infrequently, and often not for significant portions of their execution time. The traditional ways to exploit this behavior is to disable the functionality that is not being used so that the power that would normally be expended in these units is saved. There is however still the problem that the user is required to pay the cost of a chip that includes all the functionality on the chip despite the fact that only a fraction of the functionality is used at any given time.
Thus there is a need for a design of a multiprocessor chip design that executes traditional single Instruction Set Architecture (ISA) parallel programs, in which the peak resources available on the chip match more closely the instantaneous resources that are needed by the programs running on the chip.